RICH Sequencer Register
Jianchun WANG
(09/09/98)
I summarize informations related to sequencer and different readout mode below. Information
sources are Igor's document, Elliot's and my codes for readout, and my understanding.
Registers
There are Mode, Data, Phase, Status, Calibration DAC and Bias DAC registers.
Most of them are both readable and writable. To access a particular register on a particular
board (geo), one can use memory address as:
A32_VME_ZERO + geo*0x1000000 + SEQ_BASE + register_add
where A32_VME_ZERO = 0xc0000000, SEQ_BASE = 0x00080000,
and register_add will be given below for each register.
Data register: 8-bit, add = 0x0000 (pSEQ->DATA)
This gives hold time for normal readout mode and calibration mode
(Thold = T0h + Tc*Rd, where Tc = 24 ns).
For channel selection mode, it gives the channel number.
For direct access mode, it includes hold, shift_in, ck, dreset, dac_on from bit 0 to bit 4.
Mode register: 8-bit, add = 0x0040 (pSEQ->MODE)
Bits[2..0] determine sequencer operation mode: (MODE_BIT_MASK)
- 000 - passive mode (SEQ_PASSIVE)
- 001 - normal readout mode (SEQ_NORMAL)
- 010 - assert/DRESET (VA_RICH_RESET) reset VA_RICH multiplexer
- 011 - channel select mode (SEQ_CHANNEL)
- 100 - calibration mode (SEQ_CALIBRATION)
- 101 - direct access mode (SEQ_DIRECT)
- 110 - flash readout mode (SEQ_FLASH)
- 111 - assert/CK and CK (SEQ_INCR_CHANNEL)
Bit[3] enable the calibration pulse generator. (CAL_PULSE_ENABLE)
Bit[4] determines if VA-RICH are in test mode. <VA_RICH_TEST)
Bit[5] soft reset of sequencer. (SEQ_RESET)
Bit[6] soft trigger which gives simultion of hardware trigger. (SEQ_TRIGGER)
Bit[7] hardware tirgger mask. (HARD_TRIGGER_ENABLE)
Phase register: 8-bit, add = 0x0800 (pSEQ->PHASE)
This provdes the phase shift between VA-RICH clock(CK) and ADC clock,
in addition to 3 cycle pipeline delay.
Status register: 8-bit, add = 0x0c00 (pSEQ->STATUS)
Bit[0] indicates that there is a HOLD signal during flash readout. ( HOLD_IN_FLASH)
Bit[1] indicates it is quite mode. (SEQ_QUITE)
Calibration DAC register: 12-bit, add = 0x0100 (pSEQ->CALDAC)
Bias DAC register: 16 x 8-bit, add = 0x0180 + step_0004
Bias DAC provides value for Vfp1-3, Vfs1-3,Vref1-3, Voffset1, Voffset2.
Normal readout mode
Normal readout mode will be the read data readout mode. When we perform pedestal measurement
or noise measure, we add software simulation for the real trigger.
To run normal readout, the program first initialize the sequencer, and then trigger many events.
Following code is performed on each board for initialization.
<![CDATA[
pSEQ->DATA = data;
pSEQ->PHASE = phase;
pSEQ->MODE = VA_RICH_RESET;
pSEQ->MODE = SEQ_NORMAL | SEQ_RESET;
pSEQ->MODE = SEQ_NORMAL;
pSEQ->MODE = SEQ_NORMAL | HARD_TRIGGER_ENABLE;
]]>
For event triggering, the program will set TIM momery if TIM exists,
<![CDATA[
pTIM = (TIM*)(TIM_addr + SHORT_IO_START);
pTIM->arm_software_trigger = 0x0001;
]]>
Or add sequecer mode with software trigger by code
<![CDATA[
pSEQ->MODE |= SEQ_TRIGGER;
]]>
The time between events varies. 6 events per second provides more than enough
time for the system.
Alternative calibration mode
This mode injects a calibration signal into a channel out of 128. Then hold
the signal at proper time and perform a normal readout.
At the beginning, the calibration pulse height is properly set up and wait
for a while till it is stable.
<![CDATA[pSEQ->CALDAC = value]]>
Then select a channel into which you want to inject signal. The sequencer
will fullfil this task while the program running following codes.
<![CDATA[
pSEQ->DATA = channel;
pSEQ->PHASE = 0x0;
pSEQ->MODE = SEQ_CHANNEL | VA_RICH_TEST | SEQ_RESET;
pSEQ->MODE = SEQ_CHANNEL | VA_RICH_TEST;
pSEQ->MODE = SEQ_CHANNEL | VA_RICH_TEST | SEQ_TRIGGER;
while(pSEQ->MODE & SEQ_TRIGGER)
{
for( i = 0; i < 10; i++)
{
/* Just waiting. When the channel selection finished,
SEQ_TRIGGER bit will be reset */
}
}
]]>
After channel selected, the program set sequencer to calibration enable normal
readout mode before it trigger a event like normal readout.
<![CDATA[
pSEQ->DATA = data;
pSEQ->PHASE = phase;
pSEQ->MODE = SEQ_NORMAL | VA_RICH_TEST | CAL_PULSE_ENABLE;
pSEQ->MODE = SEQ_NORMAL | VA_RICH_TEST | CAL_PULSE_ENABLE | HARD_TRIGGER_ENABLE;
]]>
Unlike normal readout or full calibration, the alternative modes need channel selection
and mode setting for each event.
Flash readout mode
In this mode, the program which control the squencer to select a channel at beginning,
then set into flash readout mode, inject signal and readout the signal shape.
The differences between this mode and alternative calibration are: There may or may not be
a hold signal. If there is no hold signal, the signal readout contains the time evolution;
During reading out, the multiplexer receives no CK, so actually signal from one channel
is sampled for 128 times at different time.
To select channel, and readout signal, the code are same as alternative mode though
the squencer performs different during readout. To select flash readout mode, the
codes are:
<![CDATA[
if (pSEQ->STATUS & HOLD_IN_FLASH)
{
pSEQ->DATA = data;
}
pSEQ->PHASE = phase;
pSEQ->MODE = SEQ_FLASH | VA_RICH_TEST | CAL_PULSE_ENABLE | HARD_TRIGGER_ENABLE;
]]>
Full calibration mode
In this mode, the ADC clock is quite slow. The sequencer selects a channel and
injects signal to it and readout one sample, then the next channel. If it had
a faster ADC clock which take 128 sample, it would be a flash readout with hold
signal channel by channel.
The channel selection is fullfiled by sequencer. The daq code need not and can not
control it. Because of this, the code does not need to set the mode every events.
So at the beginning, the code is as following. I put time delay between each command,
though they may not be necessary.
<![CDATA[
pSEQ->DATA = data;
pSEQ->PHASE = phase;
pSEQ->MODE = VA_RICH_RESET;
pSEQ->MODE = SEQ_CALIBRATION | SEQ_RESET;
pSEQ->MODE = SEQ_CALIBRATION | VA_RICH_TEST;
pSEQ->MODE = SEQ_CALIBRATION | VA_RICH_TEST | CAL_PULSE_ENABLE;
]]>
Then the code setups CALDAC and sends many triggers.
Wire pulser calibration mode
Eventually, we will use a module to send signal into the anode wire, and trigger
the event like the real event. At this moment, we do not have all ready. What
we did is something like alternative calibration. The DAC_ON digital signal
will generate a signal to anode wire. At the VA-RICH chip part, we did not
set test_on. Thus only induced signal from anode wire will be detected.
The code to set up this mode is following:
<![CDATA[
pSEQ->DATA = data;
pSEQ->PHASE = phase;
pSEQ->MODE = SEQ_NORMAL | CAL_PULSE_ENABLE;
pSEQ->MODE = SEQ_NORMAL | CAL_PULSE_ENABLE | HARD_TRIGGER_ENABLE;
]]>
Other than this, the code is exactly the same as alternative calibration.
Be sure that the DAC_ON signal is connected to anode wire.
Send your comments to: J.C.Wang